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Target Connection: Bare-Metal and Driver Debug
The ARM DSTREAM
DSTREAM
TM
Debug and Trace Unit provides
Specification
DS-5 Debugger with high-performance low-level debug and
trace connection to hardware targets.
DSTREAM enables DS-5 Debugger to bring up a platform
and debug bare metal software in stop-mode, with full
access to the processor and system resources.
Thanks to its large buffer DSTREAM supports long-term
off-chip trace. This enables the debug of complex, time-
related software bugs, and performance optimization of
Debug Interface
JTAG Speed
Download
Trace Buffer
Trace Speed
Trace Frequency
JTAG and Serial-Wire Debug
60 MHz
2.5 MB/s
4 GB
600 Mbps/pin (16-bit)
300 MHz DDR
critical code.
DSTREAM features.
DS-5 Configuration Database
DS-5 provides pre-configured JTAG and trace for
catalogue devices. Just choose a device on the Debug
Configurations dialog to connect the debugger to one of
these targets.
The default DS-5 configuration database is stored on
<install_directory>\sw\debugger\configdb . However,
you can add custom configuration databases by selecting
Window ? Preferences ? DS-5 ? Target Database.
Debugging Custom Devices
The tools required to bring-up new SoCs and boards, and
Clear visual indicators for
target status
DSTREAM connection
to Mistral EVM
USB 2.0 or Ethernet
connection to host
1 V to 5V target interface,
configurable by target
Direct target connection
for optimal signal integrity
add them to the configuration database are provided in the
DS-5 installation:
CSAT
Debug
n : This command line-based tool enables manual
control of the registers of a CoreSight Debug Access
Port and script access to the IP blocks connected to it.
n Hardware Configuration: This graphical
utility reads the contents of a CoreSight ROM Table to
auto-configure the target connection. It also enables
Low-Level Debug Features
DS-5 Debugger implements support for the latest ARM
processors and technology:
n
Multi-core debug: DS-5 supports AMP and SMP
configurations, as well as big.LITTLE systems
Linux
n kernel awareness: visualize and access kernel
threads and modules on single and multi-core targets
manual configuration if the table is incorrectly set up.
n
Hypervisor
debug: access memory in hypervisor
ConfigDB
Import: Use it to import the new debug
mode and set virtual machine-dependent breakpoints
hardware configuration into a configuration database.
Direct
n
memory access: using the AHB-AP port of
This utility outputs DTSL Python scripts (.py), which
can be used to manually modify the configuration of each
IP block with a simple scripting language.
the CoreSight DAP for fast memory download and
debug of running systems.
4
DS-5 Quick Start Guide
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